Effect of mask discretization on performance of silicon arrayed waveguide gratings

We studied the impact of the lithography mask discretization on silicon arrayed waveguide grating (AWG) performance. When we decreased the mask grid from 5 to 1 nm, we observed an experimental improvement in crosstalk of 2.7-6 dB and cumulative crosstalk improvement of 1.2-5 dB, depending on the wavelength channel spacing and the number of output channels. We demonstrate the effect for the AWGs with 200-and 400-GHz channel spacing, with 4, 8, and 16 output wavelength channels. With 1-nm mask grid, the average crosstalk is -26 and -23 dB for 400- and 200-GHz devices, respectively. This is the lowest crosstalk for silicon AWGs reported to the best of our knowledge. A simulation study is performed by looking specifically at phase errors due to mask grid snapping (ignoring other phase error sources), which shows an expected improvement in crosstalk of 12 dB

High-Q photonic crystal nanocavities on 300 mm SOI substrate fabricated with 193 nm immersion lithography

On-chip 1-D photonic crystal nanocavities were designed and fabricated in a 300 mm silicon-on-insulator wafer using a CMOS-compatible process with 193 nm immersion lithography and silicon oxide planarization. High quality factors up to 10(5) were achieved. By changing geometrical parameters of the cavities, we also demonstrated a wide range of wavelength tunability for the cavity mode, a low insertion loss and excellent agreement with simulation results. These on-chip nanocavities with high quality factors and low modal volume, fabricated through a high-resolution and high-volume CMOS compatible platform open up new opportunities for the photonic integration community

Room Temperature InP DFB Laser Array Directly Grown on (001) Silicon

Fully exploiting the silicon photonics platform requires a fundamentally new approach to realize high-performance laser sources that can be integrated directly using wafer-scale fabrication methods. Direct band gap III-V semiconductors allow efficient light generation but the large mismatch in lattice constant, thermal expansion and crystal polarity makes their epitaxial growth directly on silicon extremely complex. Here, using a selective area growth technique in confined regions, we surpass this fundamental limit and demonstrate an optically pumped InP-based distributed feedback (DFB) laser array grown on (001)-Silicon operating at room temperature and suitable for wavelength-division-multiplexing applications. The novel epitaxial technology suppresses threading dislocations and anti-phase boundaries to a less than 20nm thick layer not affecting the device performance. Using an in-plane laser cavity defined by standard top-down lithographic patterning together with a high yield and high uniformity provides scalability and a straightforward path towards cost-effective co-integration with photonic circuits and III-V FINFET logic

Low-power, 10-Gbps 1.5-Vpp differential CMOS driver for a silicon electro-optic ring modulator

We present a novel driver circuit enabling electro-optic modulation with high extinction ratio from a co-designed silicon ring modulator. The driver circuit provides an asymmetric differential output at 10Gbps with a voltage swing up to 1.5V(pp) from a single 1.0V supply, maximizing the resonance-wavelength shift of depletion-type ring modulators while avoiding carrier injection. A test chip containing 4 reconfigurable driver circuits was fabricated in 40nm CMOS technology. The measured energy consumption for driving a 100fF capacitive load at 10Gbps was as low as 125fJ/bit and 220fJ/bit at 1V(pp) and 1.5V(pp) respectively. After flip-chip integration with ring modulators on a silicon-photonics chip, the power consumption was measured to be 210fJ/bit and 350fJ/bit respectively

Co-integration of Ge detectors and Si modulators in an advanced Si photonics platform

A Si photonics platform is described, co-integrating advanced passive components with Si modulators and Ge detectors. This platform is developed on a 200mm CMOS toolset, compatible with a 130nm CMOS baseline. The paper describes the process flow, and describes the performance of selected electro-optical devices to demonstrate the viability of the flow